Table of Contents
Microblaze and NIOS performance (OLD Xilinx FAQ)
19. What is the MicroBlaze performance? How many Dhrystone MIPS can it achieve? MicroBlaze is the industry's fastest soft procesor core for FPGAs. It can deliver up to 123 Dhrystone MIPS (D-MIPS) at 150 MHz in a Virtex-II Pro™ FPGA. [back to top]
20. What is the difference between the MIPS that Altera quotes for their soft processor and the Dhrystone MIPS that Xilinx quotes for the MicroBlaze™ soft processor? Nios claims one instruction per cycle (i.e., 50 MHz = 50 MIPS). This is only accurate if you are running NO-OPs. Dhrystone 2.1 is an industry standard benchmark tool that exercises the integer processing capabilities of a processor. It helps give a more meaningful comparison between processors, because, clearly all instructions cannot be executed in one cycle. We used the Dhrystone 2.1 benchmark on Nios and on MicroBlaze™ to substantiate our MicroBlaze performance claim of twice the speed.
MICROBLAZE
Xilinx unleashes the full potential of embedded FPGA designs with the MicroBlaze™ soft processor solution. The MicroBlaze core is a 32-bit Harvard RISC architecture with a rich instruction set optimized for embedded applications. The processor is a soft core, meaning that it is implemented using general logic primitives rather than a hard, dedicated block in the FPGA. The MicroBlaze soft processor is supported in the Xilinx Spartan and Virtex series of FPGAs.
The MicroBlaze solution is designed to be flexible, giving the user control of a number of features such as the cache sizes, interfaces, and execution units. The configurability allows the user to trade-off features for size, in order to achieve the necessary performance for the target application at the lowest possible cost point.
The MicroBlaze soft core is licensed as part of the Xilinx Embedded Development Kit (EDK). The EDK is a complete embedded development solution that includes a library of peripheral IP cores, the award-winning Xilinx Platform Studio™ tool suite for intuitive hardware system creation, a Built-On Eclipse software development environment, GNU compiler, debugger and more. The MicroBlaze processor is also supported by third party development tools and Real Time Operating Systems (RTOS).
aeMB
MB-Lite
OpenFIRE
OpenRISC
The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform must be versatile to fit various target applications. Platform is based on three main ingredients:
free, open source 32/64-bit RISC/DSP architecture set of free, open source implementations of the architecture complete set of free, open source software development tools, operating systems and software applications/libraries However the OpenRISC project does not impose any restrictions on third parties to create their own proprietary implementations of the OpenRISC 1000 architecture or port their own software development tools, operating systems and applications to the OpenRISC. The OpenRISC 1000 architecture is the latest in the development of modern open architectures and the base for a family of 32- and 64-bit RISC/DSP processors. Open architecture allows a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. Designed with emphasis on performance, simplicity
NIOS
LEON2
LEON2 is a 32-bit RISC SPARC V8 compliant architecture, and uses big endian byte ordering as specified in the SPARC V8 reference manual.
simekm2@vlsim /cygdrive/d/users/simekm2/leon3/grlib-gpl-1.0.10-b1640/designs
$ cd leon3-avnet-
leon3-avnet-3s1500/ leon3-avnet-ml401/
leon3-avnet-eval-xc4vlx25/ leon3-avnet-xc2v1500/
simekm2@vlsim /cygdrive/d/users/simekm2/leon3/grlib-gpl-1.0.10-b1640/designs
$ cd leon3-avnet-eval-xc4vlx25/
simekm2@vlsim /cygdrive/d/users/simekm2/leon3/grlib-gpl-1.0.10-b1640/designs/leo
n3-avnet-eval-xc4vlx25
$ make ise-synp
Scanning libraries
grlib
apa
apa3
axcelerator
altera_mf
atmel
ihp25
ec
synplify
umc
virage
unisim
techmap
fpu
opencores
gaisler
esa
gleichmann
cypress
micron
openchip
work
simekm2@vlsim /cygdrive/d/users/simekm2/leon3/grlib-gpl-1.0.10-b1640/designs/leon3-avnet-ml401
$ make help
interactive targets:
make vsim-launch : start modelsim
make ncsim-launch : compile design using ncsim
make actel-launch-synp : start Actel Designer for current project
make ise-launch : start ISE project navigator for XST project
make ise-launch-synp : start ISE project navigator for synplify project
make quartus-launch : start Quartus for current project
make quartus-launch-synp : start Quartus for synplify project
make synplify-launch : start synplify
make xgrlib : start grlib GUI
batch targets:
make vsim : compile design using modelsim
make ncsim : compile design using ncsim
make ghdl : compile design using GHDL
make actel : synthesize with synplify, place&route Actel Designer
make ise : synthesize and place&route with Xilinx ISE
make ise-map : synthesize design using Xilinx XST
make ise-prec : synthesize with precision, place&route with Xilinx ISE
make ise-synp : synthesize with synplify, place&route with Xilinx ISE
make isp-synp : synthesize with synplify, place&route with ISPLever
make quartus : synthesize and place&route using Quartus
make quartus-map : synthesize design using Quartus
make quartus-synp : synthesize with synplify, place&route with Quartus
make precision : synthesize design using precision
make synplify : synthesize design using synplify
make scripts : generate compile scripts only
make clean : remove all temporary files except scripts
make distclean : remove all temporary files